Non-volatile memory (NVM) is the general term used to describe the type of memory that retains its data even when power is turned off, and this sort of memory is typically used to store data that must not be lost when a device incorporating the memory looses power. Such devices include computers, CD-ROMs, mobile phones, digital cameras, compact flash cards, mp3 players and Micro-Controller Units (MCUs) from the automotive, aero and other industries.
Types of non-volatile memory include Read Only Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable and Programmable Read Only Memory (EEPROM), Flash EEPROMs, Non-Volatile Static Random Access Memory (NVSRAM), Ferroelectric Random Access Memory (FeRAM), and the like.
Whilst some non-volatile memory is purely “read only”, with the “programming” being done by hard-coding the data during the memory fabrication process, other types are programmed electrically post-fabrication.
One type of programmable non-volatile memory the present invention relates to is Electrically Erasable and Programmable Read Only Memory (EEPROM), however the invention may equally be applied to other non-volatile memory types listed above. Electrically Erasable and Programmable Read Only Memory (EEPROM) can be split into two sub types: byte erasable and Flash EEPROM. As the name suggests, the byte erasable type can be erased and written in byte size chunks, whilst flash memory is written in byte (or larger) sized chunks, but is erased in sections (which are multiple bytes in size). The size of the sections erased in flash memory is part specific, and can be anywhere in size from meaning the entire memory array of the device to only a sub-portion, or sector, comprising a small number of individual bytes.
EEPROMs store information by storing charge on an insulated piece of semiconductor material, known as the floating gate. Typically, the insulating material is a layer of Silicon Dioxide. As is known in the art, this charge is moved onto the insulated material forming the memory cell by either Hot Carrier Injection (HCI) or Fowler-Nordheim Tunneling (FNT). Each individual memory cell can store a single bit of information, thus they are often referred to as bitcells.
Briefly, Hot Carrier Injection (via either Hot holes, i.e. positive charges, or Hot electrons, i.e. negative charges) works by applying a large voltage bias across the channel of the bitcell, resulting in the “heating”, i.e. energy injection, of the carriers within the channel, which provides some of them with enough energy to surmount the silicon dioxide energy barrier, and thus are “injected” into the insulated material.
Meanwhile, Fowler-Nordheim tunneling works by applying a high electric field between the gate of the bitcell and either the source or drain. Assuming the field is high enough, this high electric field lowers the height of the energy barrier of the silicon dioxide layer and thus allows electrons to “tunnel” across the insulated material and onto the floating gate forming the bitcell.
While either Hot Carrier Injection or Fowler-Nordheim Tunneling may be used to move charge onto the insulated floating gate of the bitcell, charge may only be removed from the insulated floating gate by Fowler-Nordheim tunneling. When using Fowler-Nordheim tunneling to remove charge from the floating gate, opposite bias conditions need to be applied.
The movement of the charge onto or off the floating gate is known as “programming” (of the bitcell). However, “programming” does not in itself refer to a particular data state of the bitcell (1 or 0), because due to possible logical inversion at the output from the core memory array and/or the output to the data bus, the programmed state may correspond to either a logic 1 or 0. For this reason, in the following description it will be assumed that “programmed” means that charge has been stored on the floating gate, whilst “unprogrammed” means that little or no charge is stored in the floating gate.
As is known in the art, the above described physical methods used to program the bitcells are carried out by biasing the terminals of the bitcell to be programmed (or read, or erased) with the correct voltages.
Since EEPROMs can be electrically erased and reprogrammed, whilst still being able to retain information without power needing to be continually applied, they are well suited to applications that require values or other data to be permanently stored, yet updated on an ongoing basis. As a result, the memory may be cycled between programmed and erased states many times over.
Regardless of the type of EEPROM, there are a number of factors that are used to determine the equality or usefulness of the memory device. The first of these factors is the endurance of the memory device.
The number of erase/program cycles a non-volatile memory device can withstand before it no longer keeps the information correctly is called its endurance. Typical values for the endurance of a non-volatile bitcell range from 10000 to over 5 Million erase/program cycles.
Unfortunately, the erase method used in EEPROMs requires high voltages to be applied, and it is this high voltage that degrades the electrical operation of each bitcell over time. The cumulative effect of this electrical degradation results in the bitcell no longer being able to store information, and hence reduces the endurance of the memory device as a whole.
Another factor used to grade the quality of an EEPROM device is its ability to retain data. Since non-volatile EEPROMs store information by storing charge on an electrically isolated piece of semiconductor material, if the isolation is lost, or even just reduced, charge can leak out of the floating gate, resulting in loss of the data stored. The isolation is typically achieved using oxides of the semiconductor material (e.g. silicon dioxide), and any defect in this oxide can result in the aforementioned charge leakage. It is to be noted that it is the effect of erasing at high voltage that partly results in this oxide layer degradation.
Speed of electrical switching, especially in semiconductor devices, is a function of the impedance of the switching part. If the impedance is high, the speed of switching is low, whilst when the impedance is low, the speed of switching is high. This means that it is desirable to have a low read driver impedance to enable fast read access times to these EEPROM devices.
Wordline drivers influence the performance of a non-volatile memory device in two major areas. The first is read access time. Wordline drivers need to be fast to be able to charge up/discharge the wordlines for read operations. The second is that wordline drivers are operated at high voltages for the erase operation, so they need to be robust with respect to transistor wear out (via degradation of the insulation layer that isolates the floating gate from the rest of the bitcell).
Existing wordline driver circuits often combine the output transistor of the wordline driver so that it can drive all three required levels, i.e. the levels required for reading, programming and erasing the bitcells. This requires switched supplies, which compromise the impedance of the read select driver and hence the read access time.
Additionally, prior art wordline driver circuits use current biased zener stacks for wordline voltage generation during program (as the supply to the above described single driver) which limits ProgFF disturb margin on the one side or programmability on the other side. Note, during program only some of the bitcells are meant to be changed from erased to programmed state in order to achieve the desired memory pattern. However, bitcells on the same wordline see the same high voltage used for programming, which may endanger their present state. Their immunity to withstand the high voltage used to program other bitcells on the same wordline is called ProgFF disturb margin.
Also, such circuits do not have protection against bitline voltages that are too low, and they have to rely on the programmed bitcell to avoid column disturb. Moreover, such circuit techniques typically use special devices (for example, memory cells with accessible floating gates), which are difficult to port to different fabrication processes.
In essence, the prior art suffers a trade off between speed of read access time versus erase endurance, resulting in one or other of them being satisfied at the expense of the other.
Accordingly, it would be desirable to provide a wordline driver for a non-volatile memory device that improves endurance and data retention of the memory device and can also provide a reduced read impedance to improve read access times.